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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT138 3-to-8 line decoder/demultiplexer; inverting Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting FEATURES * Demultiplexing capability * Multiple input enable for easy expansion * Ideal for memory chip select decoding * Active LOW mutually exclusive outputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT138 The 74HC/HCT138 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7). The "138" features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the "138" to a 1-of-32 (5 lines to 32 lines) decoder with just four "138" ICs and one inverter. The "138" can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The "138" is identical to the "238" but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER propagation delay tPHL/ tPLH tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". An to Yn E3 to Yn En to Yn input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 12 14 3.5 67 17 19 3.5 67 ns ns pF pF HCT UNIT September 1993 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting PIN DESCRIPTION PIN NO. 1, 2, 3 4, 5 6 8 15, 14, 13, 12, 11, 10, 9, 7 16 SYMBOL A0 to A2 E1, E2 E3 GND Y0 to Y7 VCC NAME AND FUNCTION address inputs enable inputs (active LOW) enable input (active HIGH) ground (0 V) outputs (active LOW) positive supply voltage 74HC/HCT138 handbook, halfpage 1 2 3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 15 14 13 12 11 10 9 7 4 5 6 E1 E2 E3 Y5 Y6 Y7 MLB312 Fig.1 Pin configuration. Fig.2 Logic symbol. (a) (b) Fig.3 IEC logic symbol. Fig.4 Functional diagram. September 1993 3 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting FUNCTION TABLE INPUTS E1 H X X L L L L L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H OUTPUTS Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H 74HC/HCT138 Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L Fig.5 Logic diagram. September 1993 4 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay An to Yn propagation delay E3 to Yn propagation delay En to Yn output transition time +25 typ. 41 15 12 47 17 14 47 17 14 19 7 6 max. 150 30 26 150 30 26 150 30 26 75 15 13 -40 to +85 min. max. 190 38 33 190 38 33 190 38 33 95 19 16 -40 to +125 min. max. 225 45 38 225 45 38 225 45 38 110 22 19 ns UNIT 74HC/HCT138 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.6 tPHL/ tPLH ns Fig.7 tTHL/ tTLH ns Figs 6 and 7 September 1993 5 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT138 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT An En E3 UNIT LOAD COEFFICIENT 1.50 1.25 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH propagation delay An to Yn propagation delay E3 to Yn propagation delay En to Yn output transition time +25 typ. 20 18 19 7 max. 35 40 40 15 -40 to +85 min. max. 44 50 50 19 -40 to +125 min. max. 53 60 60 22 ns ns ns ns 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.7 Figs 6 and 7 UNIT VCC WAVEFORMS (V) TEST CONDITIONS September 1993 6 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer; inverting AC WAVEFORMS 74HC/HCT138 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". September 1993 7 |
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